1. Field of the Invention
The present invention relates an over-sampling D/A converter for achieving a high S/N ratio and, more particularly, an over-sampling D/A converter which has a mute function at its output portion.
2. Description of the Related Art
In recent years, in the field of the D/A converter, an over-sampling D/A converter has been developed and employed in practical use. Such over-sampling D/A converter can achieve high conversion precision at a low conversion bit number based on the over-sampling technique in which a sampling frequency fs is set sufficiently higher than a signal frequency bandwidth fB. In particular, since the D/A converter using .SIGMA. .DELTA. modulation (sigma-delta modulation) can get a sufficient S/N ratio (signal-to-noise ratio) at a relatively low over-sampling ratio, recently such D/A converter has become the mainstream of the audio D/A converter.
For example, followings may be listed as the over-sampling D/A converter. FIG. 1 is a block circuit diagram showing a configuration of the over-sampling D/A converter. As shown in FIG. 1, the D/A converter comprises a .SIGMA. .DELTA. modulator 1, a PRZ signal generator 2, and an analog filter 3. FIG. 2 is a timing chart of a clock signal CK, an NRZ (non-return-to-zero) signal, an RZ (return-to-zero) signal, an RZn signal which is a complementary signal of the RZ signal, and a PRZ (polar-return-to-zero) signal in FIG. 1. Also, average DC potentials of respective signals are shown in FIG. 2.
Such D/A converter has a function for fixing its output potential at a constant potential, i.e., a mute function, at its output portion. Normally, the constant potential is a middle point potential (VDD/2) between the potential of the power supply voltage VDD and the potential of the ground voltage GND. Because of this mute operation, abnormal sounds being generated immediately after the power supply is turned ON until the system is shifted into its normal mode by the reset operation, abnormal sounds being generated when the digital input signal is brought temporarily into its abnormal state due to mode switching of the system, and the like can be prevented. In addition, since re-quantization noises which are peculiar to the .SIGMA. .DELTA. modulator 1 shown in FIG. 1 and are generated in input of zero data can be suppressed by this mute operation, the S/N ratio can be improved.
FIG. 3 is a block circuit diagram showing a configuration of the over-sampling D/A converter having the mute function. This D/A converter is constructed by adding a mute circuit 19 to the PRZ signal generator 2 shown in FIG. 1. The mute circuit 19 is controlled by the mute signal. The mute circuit 19 is composed of an AND circuit 20 and a NAND circuit 21. The NAND circuit 21 receives an inverted signal of the mute signal and an inverted signal of the RZ signal, and then outputs an RZm signal. The AND circuit 20 receives the inverted signal of the mute signal and the RZn signal, and then outputs an RZnm signal.
Next, this mute operation will be explained with reference to FIG. 4 hereinbelow. FIG. 4 is a timing chart of the clock signal CK, the NRZ signal, the RZm signal, the RZnm signal, the PRZ signal, and the mute signal in FIG. 3. Also, average DC potentials of respective signals are shown in FIG. 4. When the mute operation is OFF, the mute signal is at the "L" level, i.e., the inverted signal of the mute signal is at the "H" level. In this case, the NAND circuit 21 outputs the input RZ signal as the RZm signal as it is. The AND circuit 20 also outputs the input RZn signal as the RZnm signal as it is. On the contrary, when the mute operation is ON, the mute signal is at the "H" level, i.e., the inverted signal of the mute signal is at the "L" level. In this case, the NAND circuit 21 outputs the RZm signal at a potential level of the power supply voltage VDD (i.e., "H" level) regardless of a value of the input RZ signal. The AND circuit 20 also outputs the RZnm signal at a potential level of the ground voltage GND (i.e., "L" level) regardless of a value of the input RZn signal. In this case, the PRZ signal which is a result of analog addition of the RZm signal and the RZnm signal is fixed at a middle point potential VDD/2 between the potential of the power supply voltage VDD and the potential of the ground voltage GND. As a result, the analog signal being output from the filter amplifier 18 can be fixed at the potential VDD/2.
FIG. 5 is a block circuit diagram showing another configuration of the over-sampling D/A converter having the mute function. In this D/A converter, an analog switch 22 for short-circuiting a feedback resistor element in a filter amplifier 18 is provided to the filter amplifier 18. Thus, a potential of the analog signal being output from the filter amplifier 18 is fixed at a reference potential of the filter amplifier 18 by opening/closing the analog switch 22. Normally, this reference potential is set at the middle point potential VDD/2 between the potential of the power supply voltage VDD and the potential of the ground voltage GND.
However, there has been a following problem in the D/A converters shown in FIGS. 3 and 5. That is, the D/A converters have had such a drawback that, if data being located near zero data are input into the .SIGMA. .DELTA. modulator 1 in FIGS. 3 and 5, an idling pattern is generated to thus produce a strong beat, as shown in FIG. 6 (J. C. Candy, "A Use of Double Integration in Sigma Delta Modulation" IEEE Trans., Commun., vol.COM-33, pp.249-258, Mar. 1985). Normally, in order to prevent this beat, a technique for adding a DC offset to the input data of the .SIGMA. .DELTA. modulator 1 in advance is employed, as shown in FIG. 7. A value which is out of a beat appearing region is selected as a DC offset value, as shown in FIG. 6, to thereby prevent generation of the beat. However, a voltage Vos of this DC offset appears at the output of the D/A converter inevitably. Thus, this voltage Vos of the DC offset causes variation of an output average DC potential of the D/A converter every ON/OFF of the above mute operation. As a result, an audible click noise is generated.
Next, variation of the output average DC potential, i.e., cause of generation of the audible click noise will be explained in detail hereinbelow. Here the explanation will be made with reference to the D/A converter shown in FIG. 3. For example, in case the zero data are input into the .SIGMA. .DELTA. modulator 1, the NRZ signal is at the "H" level (VDD) or the "L" level (GND) with a probability of 1/2. As evident from FIG. 4, it can be understood that the RZm signal becomes the "H" level (VDD) with a probability of 1/4 at the time when the mute operation is OFF. That is, the average DC potential of the RZm signal is VDD/4. A value obtained by adding the above voltage Vos to the average DC potential is input into an inverter circuit 14. Hence, an output average DC potential E1 of the inverter circuit 14 which outputs an inverted value of the above added value can be given by EQU E1=(3/4)VDD-Vos (1)
Similarly, an output average DC potential E2 of an inverter circuit 15 can be given by EQU E2=(1/4)VDD-Vos (2)
FIG. 8 shows an equivalent circuit of the above output average DC potential E1 of the inverter circuit 14, the output average DC potential E2 of an inverter circuit 15, and resistors 16, 17 (resistance value Ri) at the time of mute operation-OFF in FIG. 3. As shown in FIG. 8, when the Norton's theorem is applied sequentially, an output average DC potential E3 of the equivalent circuit, if viewed from an addition point between the resistor 16 and the resistor 17, can be given by EQU E3=(1/2)VDD-Vos (3)
If resistance values of respective resistor elements are set as shown in FIG. 9, an output average DC potential E4 of a filter amplifier 18 can be given based on the Eq. (3) as EQU E4=(1/2)VDD+A.multidot.Vos (4)
Where A=Ro/Ri'.
On the contrary, when the mute operation is ON, the RZm signal is fixed at the "H" level (VDD) and the RZnm signal is fixed at the "L" level (GND). That is, the output potential E5 of the inverter circuit 14 is at the "L" level (GND), and the output potential E6 of the inverter circuit 15 is at the "H" level (VDD). FIG. 10 shows an equivalent circuit of the output average DC potential E5 of the inverter circuit 14, the output average DC potential E6 of the inverter circuit 15, and the resistor elements 16, 17 in FIG. 3. As shown in FIG. 10, if the Norton's theorem is applied, an output average DC potential E7 of the equivalent circuit, if viewed from an addition point between two resistor elements, can be given by EQU E7=(1/2)VDD (5)
In this case, the output average DC potential E4 of the filter amplifier 8 becomes equal to the above output average DC potential E7.
In this manner, in the D/A converter shown in FIG. 3, the output average DC potential E4 of the filter amplifier 8 is set to E4=(1/2)VDD+A.multidot.Vos when the mute operation is OFF, while such output average DC potential E4 of the filter amplifier 8 is set to E4=(1/2)VDD when the mute operation is ON. As a result, as shown in FIG. 11, variation in the output average DC potential of the filter amplifier 8 is caused according to ON/OFF of the mute operation. That is, an audible click noise is generated. Such generation of the audible click noise due to ON/OFF of the mute operation is the problem which will be caused similarly in the D/A converter shown in FIG. 5.